In requied at high resolutions. The SAR ADCs on

the last two decades IC designs for signal processing applications have been
rapidly growing. So, the requirement for a low power ,small area,medium
resolution (10-12 bits) analog-to-digital converters with low-to-medium speeds
is expanding.  Flash and pipelined ADC
architectures are used for high speed conversion systems whereas SAR and sigma
delta ADCs arec used for low-to-medium speed systems.

 The flash ADC uses 2n-1 comparators for an n
bit resolution, which means the number of comparators doubles with the addition
of each 1-bit resolution. This usage of much number of comparators increase the
area occupied and the power consumed by the ADC. Hence the Flash ADC is limited
8 bits.

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The pipelined ADC architecture  is
used for video processing & wireless receivers applications. They can be
used upto a  resolution of  8-12 bits and sampling speed of 200 MS/s.. The
limitations of the architecture are high power consumption and the large switch
capacitor network requied at high resolutions.


SAR ADCs on the other hand can be designed up to 10-14 bits. The operation of
this ADC mainly depends on the digital to analog converter and the binary
search algorithm it uses. The limitations are the low speed of the SAR ADC due
to its sequential operation and the capacitor mismatches of the switched capacitor
circuit used in the DAC at high resolutions.

To overcome the limitations research
has been done on various hybrid ADC models to improve the accuracy, power, and speed. The introduced pipelined-SAR ADC
architecture improves both power and conversion efficiency but the speed of
this ADC is less compared to the SAR ADC due to the additional interstage gain
amplifier. The other limitations of this architecture are high power
consumption due to the DAC within the stage and capacitor mismatches.  The flah-SAR ADC architecture  gives an improved conversion rate without adding
additional complexity and power consumption. But, this architecture is also
limited at higher resolutions because of the higher number of comparators
required for the flash and the higher order DAC required for the SAR ADC.

This paper presents Two-Step SAR-flash ADC architecture for improved
conversion accuracy with lower power consumption and smaller area. It can
achieve a speed upto 200 MS/s without affecting the accuracy. This is a 12-bit
ADC which contains two identical 6-bit SAR-Flash ADCs connected by a interstage
gain amplifier. The 6-bit SAR-Flash ADC contains a  of 3-bit SAR ADC followed by a 3-bit flash
ADC. This improves the performance due to the reduced capacitor mismatch
effects and the less number of comparators used in the flash. The detailed
architecture with time operation of this ADC design is described in the next